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| integrated circuits inc. ap89341/170/085 a plus make your production a-plus voice otp ic a p8 9341 C 341sec a p89170 C 170sec a p89085 C 85sec a plus integrated circuits inc. sales e-mail: sales@aplusinc.com.tw address: 3 f-10, no. 32, sec. 1, chenggung rd., taipei, taiwan 115, r.o.c. (115) ???^?? 32 ? 3 ? 10. tel: 886-2-2782-9266 fax: 886-2-2782-9255 website : http: //www.aplusinc.com.tw support e-mail: service@aplusinc.com.tw
integrated circuits inc. ap89341/170/085 features standard cmos process. embedded 8m/4m/2m eprom. 341/170/85 sec voice length at 6khz sampling and 4- bit adpcm compression. maximum 254 voice groups. combination of voice blocks to extend playback dura tion. 7680 table entries are available for voice block co mbinations. user selectable pcm or adpcm data compression three triggering modes are available (controlled by m1 and m0 input pins): - key trigger mode (m1=0, m0=0) - s1 ~ s8 to trigge r up to 32 voice groups; sbt to trigger up to 254 voice groups sequentially. - cpu parallel trigger mode (m1=0, m0=1) C s[8:1] s ervices as 8-bits address to trigger up to 254 voice groups with sbt goes high t o strobe the address bits. - cpu serial command mode (m1=1, m0=0) C user comma nds are clocked serially into the chip which enable user to fully control th e operation of the chip. voice group trigger options: edge / level; hold / u n-hold; retrigger / non-retrigger. whole chip options: ramp / no-ramp; output options; long / short debounce time. optional 16ms or 65us (@ 8khz sampling rate) select able debounce time rst pin set to high to stop the playback at once three user programmable outputs for stop pulse, bus y signal and flashing led. built-in oscillator to control sampling frequency w ith an external resistor 2.2v C 3.6v single power supply and < 5ua low stand -by current pwm vout1 and vout2 drive speaker directly d/a cout pin drives speaker through an external bjt development system support voice compilation. description ap89341/170/085 series high performance voice otp i s fabricated with standard cmos process with embedded 8m/4m/2m bits eprom. it can store up to 3 41/170/85 sec voice message with 4-bit adpcm compression at 6khz sampling rate. 8-bit pcm is also available as user selectable option. three trigger modes, simple key trigger mode, paral lel cpu trigger mode and cpu serial command mode, facilitate different user interface. user se lectable triggering and output signal options provi de maximum flexibility to various applications. built -in resistor controlled oscillator, 8-bit current m ode d/a output and pwm direct speaker driving output mi nimize the number of external components. pc controlled programmer and developing software are a vailable. ver 4.0 1 may 14, 2009 integrated circuits inc. ap89341/170/085 pin names pin (24-pin) playback mode otp program mode description 1 s7 io6 trigger pin (i/o pin with internal pull-do wn) 2 s8 io7 trigger pin (i/o pin with internal pull-do wn) 3 vss vss ground 4 vout1 - pwm output to drive speaker directly 5 vout2 - pwm output to drive speaker directly 6 vdd vdd supply voltage 7 avdd avdd analog supply voltage 8 vpp vpp supply voltage for otp programming 9 osc aclk oscillator input 10 cout - d/a current output 11 avss avss analog ground 12 out3 - programmable output (i/o pin) 13 out2 sio programmable output (i/o pin) 14 out1 oeb programmable output (i/o pin) 15 rst dclk reset pin (input pin with internal pull -down) 16 sbt pgm trigger pin (i/o pin with internal pull- down) 17 m1 m1 mode select pin 1 (input with internal pul l-down) 18 m0 m0 mode select pin 0 (input with internal pul l-down) 19 ~ 24 s1~s6 io0~io5 trigger input (i/o pin with i nternal pull-down) ver 4.0 2 may 14, 2009 integrated circuits inc. ap89341/170/085 ver 5.0 3 aug 23, 2010 pin descriptions s1 ~ s8 input trigger pins: - in key trigger mode, s1 to s8 is used to trigger the first 32 out of the total 254 voice groups . - in cpu parallel command mode, s1 to s8 serve as v oice group address inputs for 254 voice groups with s1 as lsb and s8 as msb. - in cpu serial command mode, s1 is chip select (sc ) pin to initiate the command input. s2 is the serial clock (sck) pin which clocks the input c ommand and data bits into the chip. s3 is the data in (di) pin in which command and data bits are shifted input into the chip. - in otp programming mode, s1 to s8 are used as dat a i/o pins. sbt input trigger pin: - in key trigger mode, this pin is trigger pin to t rigger the playback of voice groups one by one sequentially. - in cpu parallel command mode, this pin is used as address strobe to latch the voice group address input at s1 to s8 and starts the voice play back. - in otp programming mode, this pin is used as pgm signal. vdd and avdd power supply pins: these two pins must be connecte d together to the positive power supply. vss and avss power ground pins: these two pins must be connecte d to the power ground. m0 and m1 operating mode setting pins: - m1=0, m0=0 set the chip into key trigger mode - m1=0, m0=1 set the chip into cpu parallel command mode - m1=1, m0=0 set the chip into cpu serial command m ode - m1=1, m0=1 set the chip into otp programming mode vout1 and vout2 digital pwm output pins which can drive speaker and buzzer directly for voice playback. osc during voice playback, an external resistor is conn ect between this pin and the vdd pin to set the sampling frequency. in otp programming mode, this is the aclk input signal. vpp during voice playback, this pin must be connected t ogether with vdd to the positive power supply voltage. in otp programming mode, this pin is conn ected to a separate 6.5v power supply voltage for eprom programming. out1, out2 and out3 - in key trigger mode and cpu parallel command mode , these pins are user programmable pins for the stop pulse, busy and led signals. - in cpu serial command mode, out1, out2 and out3 a re fixed as busy, pout and full status output which tell the status of the chip ope ration. pout can be further configurable to busyb, 8k, 4k, 2k, 1k, 16hz, 1m and empty (or fullb ). - during otp programming, out1 serves as oeb while out2 serves as sio (serial data io). cout analog 8-bit current mode d/a output for voice play back rst chip reset in playback mode or dclk pin in otp prog ramming mode. integrated circuits inc. ap89341/170/085 ver 5.0 4 aug 23, 2010 voice section combinations voice files created by the pc base developing syste m are stored in the built-in eprom of the ap89341/170/085 chip as a number of fixed length vo ice blocks. voice blocks are then selected and grouped into voice groups for playback. up to 254 voice groups are allowed. a voice block table is used to store the information of combinations of voice blocks and then group them together to form voice group. chip ap89341 ap89170 AP89085 memory size 8m bits 4m bits 2m bits max no. of voice block 2016 992 480 max. no. of voice group 254 254 254 no of voice table entries 7680 7680 7680 voice length (@ 6khz 4-bit adpcm) 341 sec 170 sec 85 sec example of voice block combination assume here we have three voice files, they are ho w are you?, sound effect and music. each of the voice file is divided into a number of fixed le ngth voice block and stored into the memory. voice file 1 - how are you? is stored in voice bl ock b0 to b12. voice file 2 - sound effect is stored in voice bloc k b13 to b15. voice file 3 - music is voice block b16 to b40. voice blocks are grouped together using voice table to form voice group for playback: group no. voice group contents voice table entries group 1 how are you? b0 b12 group 2 sound effect + how are you? b13 b15 + b 0 b12 group 3 how are you? + music b0 b12 + b16 b40 group 4 music b16 b40 voice data compression voice file data is stored in the on-chip eprom as e ither 4-bit adpcm or 8-bit pcm format. voice data stored as 4-bit adpcm provides 2:1 data compre ssion which can save 50% of memory space. on the other hand, voice data are stored as 8-bit p cm format means no data compression is employed but voice playback quality will be better. integrated circuits inc. ap89341/170/085 ver 5.0 5 aug 23, 2010 programmable options in key trigger mode (m1=0; m0=0) and cpu parallel t rigger mode (m1=0; m0=1), user can select different trigger functions and output signals to b e sent out from the pins out1, out2 and out3. options that affect all voice group playback are ca lled whole chip options. options that only affect the playback of individual voice group are called g roup options. whole chip options long (16ms) or short (65us) debounce time at 8khz s ampling rate. ramp-up-down enable or disable: when cout is used for playback, ramp-up-down should be enabled. this function eliminates the pop noise at the begin and end of voice playback. when vout1 and vout2 are used to drive speaker dire ctly, ramp-up-down should be disabled. fig. 1 ramp-up-down enable fig.2 ramp-up-do wn disable output options: this option sets up the three output pins out1, out 2 and out3 to send out different signals during voice playback. four settings are allowed: out1 out2 out3 option 1 led1 led2 busy option 2 stop led1 led2 option 3 led1 busy stop option 4 led1 busy busyb note: busy can be set or reset associated with each voice block. stop plus must be set to enable in order to have stop plus to come out at th e end of playback. fig. 3 output waveforms integrated circuits inc. ap89341/170/085 ver 5.0 6 aug 23, 2010 group options user selectable options that affect each individual group are called group options. they are: edge or level trigger unholdable or holdable trigger re-triggerable or non-retriggerable stop pulse disable or enable fig. 4 to fig. 9 show the voice playback with diffe rent combination of triggering mode and the relationship between outputs and voice playback. fig. 4 level, unholdable, non-retriggerable fig. 5 level holdable fig. 6 sbt sequential trigger with level holdable and unholdable integrated circuits inc. ap89341/170/085 ver 5.0 7 aug 23, 2010 fig. 7 edge, unholdable, non-retrigger fig. 8 edge, holdable fig. 9 sbt sequential trigger with edge holdable a nd unholdable trigger modes there are three trigger modes available for ap89341 /170/085 series which are determined by setting m1 and m2 pins to logic high or low. key trigger mode (m1=0; m0=0); cpu parallel trigger mode (m1=0; m0=1); cpu serial command mode (m1=1; m0=0); integrated circuits inc. ap89341/170/085 ver 5.0 8 aug 23, 2010 key trigger mode (m1=0, m0=0) with this trigger mode, the beginning 32 voice grou ps are triggered by setting s1 to s8 to hihg or low in different combinations. each voice group ca n have its only independent trigger options (see fig. 4, 5, 7 and 8 for trigger options definition). a maximum of 254 voice groups are available. the 3 3rd to 254th voice groups can only be triggered one by one sequentially with the sbt key (see fig. 6 and 9). the setting of s1 to s8 for triggering the 1st to t he 32nd voice groups are as follow: voice group s1 s2 s3 s4 s5 s6 s7 s8 1 high nc nc nc nc nc nc nc 2 nc high nc nc nc nc nc nc 3 nc nc high nc nc nc nc nc 4 nc nc nc high nc nc nc nc 5 nc nc nc nc high nc nc nc 6 nc nc nc nc nc high nc nc 7 nc nc nc nc nc nc high nc 8 nc nc nc nc nc nc nc high 9 high high nc nc nc nc nc nc 10 nc high high nc nc nc nc nc 11 nc nc high high nc nc nc nc 12 nc nc nc high high nc nc nc 13 nc nc nc nc high high nc nc 14 nc nc nc nc nc high high nc 15 nc nc nc nc nc nc high high 16 high nc nc nc nc nc nc high 17 high high high nc nc nc nc nc 18 nc high high high nc nc nc nc 19 nc nc high high high nc nc nc 20 nc nc nc high high high nc nc 21 nc nc nc nc high high high nc 22 nc nc nc nc nc high high high 23 high nc nc nc nc nc high high 24 high high nc nc nc nc nc high 25 high high high high nc nc nc nc 26 nc high high high high nc nc nc 27 nc nc high high high high nc nc 28 nc nc nc high high high high nc 29 nc nc nc nc high high high high 30 high nc nc nc nc high high high 31 high high nc nc nc nc high high 32 high high high nc nc nc nc high note: nc represents open or no connection integrated circuits inc. ap89341/170/085 ver 5.0 9 aug 23, 2010 cpu parallel trigger mode (m1=0, m0=1) in this mode, s8 to s1 serve as 8-bit addresses inp ut for 254 voice groups with s8 represents the msb and s1 represents lsb. after group address is s et and ready, setting the sbt input pin to high will trigger the corresponding voice group to playb ack. trigger options defined in fig. 4, 5, 7 and 8 are v alid for this mode. fig. 10 cpu parallel trigger mode note that sbt pin cannot be used as single button s equential trigger in this mode. in stead, it acts as a strobe input to clock-in the voice group address set at s8 to s1 into the chip. voice groups are represented in binary address form at. for example: s[8:1] = 0000 0000 (00hex) for voice group #1 s[8:1] = 0000 0001 (01hex) for voice group #2 ? ? ? s[8:1] = 0000 1000 (08 hex) for voice group #9 ? ? ? s[8:1] = 1000 1000 (88 hex) for voice group #137 ? ? ? s[8:1] = 1111 1101 (fd hex) for voice group #254 cpu serial command mode (m1=1, m0=0) this trigger mode is specially designed for simple cpu interface. the ap89341/170/085 is controlled by command sent to it from the host cpu. s1 to s3 are used to input command word into the chip while out1 to out3 as output from the chip to the h ost cpu for feedback response. s1 acts as cs (chip select) to initiate the command word input s2 acts as sck (serial clock) to clock-in the comma nd word at rising edge. s3 acts as di (data-in) to input the command bits. out1 acts as busy to indicate the chip is in busy s tate. out2 acts as pout to output user selected informati on. out3 acts as full signal to indicate the voice grou p address buffer is full. command input into the chip may contains 8-bit or 1 6-bit data. the first 8-bit data is command bits while the second 8-bit data (if any) is the voice g roup address data. table 1 summarize the available commands and their functions. integrated circuits inc. ap89341/170/085 ver 5.0 10 aug 23, 2010 command d7 d6 d5 d4 d3 d2 d1 d0 description pup1 (c5h) 1 1 0 0 0 1 0 1 power up the chip with no ramp-up (suitable for vout direct drive) pup2 (8dh) 1 0 0 0 1 1 0 1 power up the chip with ramp-up (suitable for cout transistor drive) pdn1 (e1h) 1 1 1 0 0 0 0 1 power down the chip with no ramp-down (suitable for vout direct drive) pdn2 (a9h) 1 0 1 0 1 0 0 1 power down the chip with ramp-down (suitable for cout transistor drive) 1 1 1 0 0 0 1 1 set output status for out2 pin status (e3h) 0 0 0 1 0 g2 g1 g0 out2 = busyb (000), 8k (001), 4k, 2k, 1k, 16hz, 1m, empty (fullb) pause (39h) 0 0 1 1 1 0 0 1 pause the playback and hold at current cout value resume (1dh) 0 0 0 1 1 1 0 1 resume playback from the previous cout value 0 1 1 1 0 0 0 1 pre-load voice group address into buffer for next playback prefetch (71h) g7 g6 g5 g4 g3 g2 g1 g0 voice group address (g7=msb; g0=lsb) power up with ramp-up (pu2-c5h) or without ramp-up (pu1-8dh) fig. 11 power-up command timing 1. pu1 (c5h) will power-up the chip and set the cou t to 80h immediately and stay there. 2. pu2 (8dh) will ramp-up chip and ramp-up cout fro m 00h to 80h and stay there. 3. power-up will start after 350us (at 6khz samplin g rate). 4. voice will be playback immediately after pu1 / p u2 completes if the section buffer is filled with the prefetch command before power-up . 5. out1 (busy) will output logic high during ramp-u p operation. 6. pdn2 (power-down with ramp-down) will be execute d correctly only if pu2 is executed before. integrated circuits inc. ap89341/170/085 ver 5.0 11 aug 23, 2010 power-down with ramp-down (pd2-a9h) or without ramp -down (pd1-e1h) fig. 12 power-down commands timing 1. pdn1 will power-down the chip and set the cout d ata to 00h immediately. 2. pdn2 will power-down the chip by ramp-down the c out from its current value to 00h. 3. power-down will start after 350us (at 6khz sampl ing rate). 4. the out1 pin (busy) will output logic high durin g ramp-down operation. 5. pdn2 (power-down with ramp-down) will be execute d correctly only if pu2 is executed before. set out2 pin status (status-e3h) fig. 14 setup the status of programmable output pi n, out2 1. signal output from the pin, out2, is defined by g[3:0], as below: g[3:0] out2 g[3:0] out2 000 busyb 100 1khz 001 8khz 101 16hz 010 4khz 110 1mhz 011 2khz 111 fullb 2. if the status is not executed, default value of out2 is the internal reset signal. 3. busyb is the logical inversion of busy. 4. empty (or fullb) is the logical inversion of ful l. 5. only the 1mhz clock will not be stopped by the p ause command. integrated circuits inc. ap89341/170/085 ver 5.0 12 aug 23, 2010 pause and resume (pause-39h; resume-1dh) fig. 15 pause and resume command timing 6. in pause state, vout1 and vout2 will stay at log ic low while the cout will stay at the current d/a data level (i.e. cout is kept outpu tting an dc current). when resume, the cout data will continue at the current d/a data level. 7. the pause state will be released by pdn1, pdn2 a nd resume commands. prefetch voice group address (prefetch-71h) fig. 16 prefetch next voice group timing 1. the prefetch command pre-load the next voice gro up address into the address buffer. 2. the out3 output (full) will become logic hihg on ce the group address is successfully loaded. 3. the voice group will be played once the playing of the current voice group is finished. 4. the full signal will become logic low once the v oice group is played and the address buffer is released and ready for next prefect actio n. 5. using the prefect make sure there is no gap betw een each voice group. integrated circuits inc. ap89341/170/085 ver 5.0 13 aug 23, 2010 block diagram fig. 17 block diagram absolute maximum ratings symbol rating unit v dd - v ss -0.5 ~ +3.8 v v in v ss - 0.3 integrated circuits inc. ap89341/170/085 ver 5.0 15 aug 23, 2010 timing waveforms fig. 18 timing waveform t sck c full s2(sck) busy cout s3(di) s1(cs) cpu serial command t c s t d h t d s t sck w t c h t cout d t f d t b d t bh s1~s8, sbt stop cout busy t b d t b h t stp w t stp d t k d cpu parallel key trigger t sbt w addr. s1~s8 sbt t a h t as t kdd integrated circuits inc. ap89341/170/085 ver 5.0 16 aug 23, 2010 ac characteristics ( t a = 0 to 70 , v dd = 3.3v, v ss = 0v, 8khz sampling ) symbol parameter min. typ. max. unit note t kd key trigger debounce time (long) 16 ? ? ms 1,2 t kd key trigger debounce time (long) C retrigger option 24 ? ? ms 1,2 t kd key trigger debounce time (short) 65 ? ? s 1,2 t kd key trigger debounce time (short) C retrigger option 200 ? ? s 1,2 t kdd key trigger delay after ramp down 256/fs ? ? s 4 t stpd stop pulse output delay time ? ? 256 s t stpw stop pulse width ? 64 ? ms 1 t bd busy signal output delay time ? ? 100 ns t bh busy signal output hold time ? 100 ? ns t as address set-up time 100 ? ? ns t ah address hold time 100 ? ? ns t sbtw sbt stroke pulse width (long) 16 ? ? ms 1,2 t sbtw sbt stroke pulse width (short) 65 ? ? s 1,2 t cs chip select set-up time 100 ? ? ns t ch chip select hold time 100 ? ? ns t ds data-in set-up time 100 ? ? ns t dh data-in hold time 100 ? ? ns t sckw serial clock pulse width 1 ? ? s t sckc serial clock cycle time 2 ? ? s t coutd cout output delay time ? ? 256 s t fd full signal output delay time ? 100 ? ns t ledc led flash frequency ? 3 ? hz 3 notes : 1. this parameter is inversely proportional to the sampling frequency. 2. the long or short debounce time is selectable as whole chip option during voice files compiling. 3. this parameter is proportional to the sampling f requency. 4. fs is sampling frequency in hz integrated circuits inc. ap89341/170/085 ver 5.0 17 aug 23, 2010 oscillator resistance table sampling frequency r osc r osc sampling frequency khz kohm kohm khz 4.90 300 140 11.00 5.26 290 130 11.76 5.88 280 120 12.50 6.09 270 110 13.33 6.33 260 100 14.51 6.67 250 91 15.63 6.85 240 82 16.95 7.14 230 75 18.18 7.46 220 68 19.23 7.70 210 62 20.83 8.06 200 56 22.22 8.47 190 51 23.81 8.93 180 43 25.00 9.26 170 9.80 160 10.42 150 note: the data in the above tables are within 3% ac curacy and measured at v dd = 3.0v. oscillator frequency is subjected to ic lot to lot variation. integrated circuits inc. ap89341/170/085 ver 5.0 18 aug 23, 2010 typical applications key trigger mode fig. 22 using 3.3v battery fig. 23 using 4.5v battery vdd, avdd,vpp vss, avss 4.5v rst s1 s2 s3 s8 sbt osc 0.1uf c r os c t cout 8 1/4 speaker 8 / 16 speaker vout1 vout2 out1 ht7335 output driving of ht ldo: ht7136 (30ma, 3.6v) ht7133 (30ma, 3.3v) ht7536 (100ma, 3.6v) ht7335 (250ma, 3.5v) ? ? ? ? ? ? rb 1k vdd, avdd,vpp vss, avss 3.3v rst s1 s2 s3 s8 sbt osc 0.1uf c r os c t cout rb 8 1/4w speaker 8 / 16 speaker vout1 vout2 out1 ? ? ? ? ? ? 1k integrated circuits inc. ap89341/170/085 ver 5.0 19 aug 23, 2010 cpu parallel mode fig. 24 5v cpu control with cout note: 1. c1 is capacitor from 0.1uf to 4.7uf depends on t he kind of vdd source and sound loudness. 2. rb is base resistor from 120 ohm to 390 ohm depe nds on vdd value and transistor gain. 3. t is an npn transistor with beta larger than 150 . 4. reference value for the above components are c = 2.2uf, rb = 390 ohm and t = 8050d. 5. refer to the oscillator resistor table for suita ble value of rosc. integrated circuits inc. ap89341/170/085 ver 5.0 20 aug 23, 2010 cpu serial command mode fig. 25 5v cpu control with tda power amplifier vdd, avdd,vpp vss, avss rst out1 out3 osc 0.1uf 10uf r osc cout 8 speaker ht7335 s1 (cs) s2 (sck) s3 (di) vout=+3.5v cs sck di busy full vin=+5v rin 2 7 0.1u 0.1u 4.7 4.7 10u 0.01uf 8 6 10uf 10k 33 5 4 gnd vcc + + -- 1 3 tda2822m mcu rin = 860k x (vin-vout) / vout integrated circuits inc. ap89341/170/085 ver 5.0 21 aug 23, 2010 bonding pad diagrams notes: 1. two vpp pads should be connected to the positive power supply during voice playback. 2. vdd and avdd should be connected to the positive power supply. 3. vss and avss should be connected to the power gn d. 4. substrate should be connected to the power gnd. a p89341 integrated circuits inc. ap89341/170/085 ver 5.0 22 aug 23, 2010 notes: 5. vpp and vsl pads should be connected to the posi tive power supply during voice playback. 6. vdd and avdd should be connected to the positive power supply. 7. vss and avss should be connected to the power gn d. 8. substrate should be connected to the power gnd. a p89170 a p89085 integrated circuits inc. ap89341/170/085 ver 5.0 23 aug 23, 2010 packages dimension outlines 24-pin 300mil p-dip package 28-pin 300mil sop package |
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